I research circuits and systems with my primary interest being power efficiency. The best way to review my past publications is Google Scholar.

Recent Work

"On the temperature dependence of subthreshold currents in MOS electron inversion layers, revisited", ISCAS 2016 (Dataset and references): The extracted data from Card et al.

"Reverse Engineering a Passive UHF RFID Tag", RFID IEEE 2016 (Presentation): The presentation from my tutorial of reverse engineering a RFID tag from the EPC Gen2 specification.

"Low-power, serial interface for power-constrained devices", MWSCAS 2015 (Supporting SPI clock data): The waveforms and matlab to generate the plots in the paper.

"A 45 μW Bias Power, 34 dB Gain Reflection Amplifier Exploiting the Tunneling Effect for RFID Applications", RFID 2015 (Esaki diode data): I extracted data and created a model generator for Esaki diodes.

"Assessing Trends in Performance per Watt for Signal Processing Applications", TVLSI 2015. (datasets and description): The "powerwall" has been reached, meaning that transistor scaling no longer helps throughput. We conducted a survey of processors, and Stanford's CPUDB shows that for SPECInt, you do not have any improvements without increases in cache for score per Watt.

ICQ 2014 (poster): I presented an asynchronous FPGA that uses power performance as a metric instead of speed.

ISSNE 2014 (poster): Address Event Representation (AER) requires two things to be effective: sparse coding and a standard interface. Sparse coding has been largely ignored by the neuromorphic community. We presented a biologically inspired AER scheme for sparse coding.